This invention lies in the field of physiological stimulating devices and, more particularly, demand-type cardiac pacemakers adapted for low power operation. The pacemaker of this invention is distinguished by its use of I.sup.2 L circuitry in low current drain configurations.
Cardiac pacers are today widely known and utilized in many regions of the world. Since the founding of the pacemaker industry, there has been an evolution of a number of different types of pacemakers in terms of the functions performed and also in terms of the technology utilized. To date, most pacemakers have utilized analog circuitry, wherein the linear transistor is the main building block. More recently the pacemaker industry has introduced some "digital" models, utilizing digital circuitry for generating the stimulus pulses and for carrying out various desired pacer functions which have been incorporated in more sophisticated pacemaker designs. Digital circuitry has gained acceptance particularly in the area of programmable pacers. Another non-functional classification of pacemakers involves the particular structure or means of embodiment of the circuitry. Thus, early pacemakers utilized only discrete element design. This has been followed by hybrid models, incorporating integrated circuits together with discrete components. The next step beyond this, to which the industry is turning its attention, is the "monolithic" pacer, wherein virtually all or most all of the circuitry is embodied on a single chip, or several chips.
The analog circuits which have been utilized in past pacemaker designs have a proven reliability and effectiveness. This reliability is, of course, highly desirable for pacemaker devices which must be designed in anticipation of lifetimes of 10 and more years. At the same time, the flexibility of digital circuits has proven itself well, and is particularly adapted for use with programmable pacers where data must be stored and a great many complex logic functions must be carried out. However, the additional complex digital circuitry that is desired is generally achieved only at the cost of greater power consumption. While improved power sources, and the lithium battery in particular, make it possible to handle the power requirements of increased logic circuitry, it remains a fundamental design objective to provide a pacer with the lowest possible overall power consumption. There is thus a fundamental need in the pacemaker art to provide a pacemaker design which incorporates the reliability and effective simplicity of analog circuits in combination with the flexibility of digital circuits, while maintaining very low power operation.
The pacemaker circuit of this invention utilizes a combination of Integrated Injection Logic (I.sup.2 L) technology in combination with linear transistor circuitry. The disclosed pacemaker is of the monolithic chip type, in that essentially all of the circuitry is provided on one chip which includes the I.sup.2 L gates, the linear transistors and most of the resistors. High value resistors and capacitors cannot be provided on the chip. A typical chip is made up of different sections, or regions, including a region devoted to an array of quad-output I.sup.2 L gates and a region comprised of bipolar NPN and PNP transistors as well as resistors. In the drawings presented with this specification, the conventional designations of multiple collector linear transistors and I.sup.2 L gates are used. Reference is made to the technical literature dealing with I.sup.2 L technology and designs. This literature provides extensive disclosures of the basic I.sup.2 L gate, operating characteristics of I.sup.2 L gates, I.sup.2 L logic design, and the general utilization of chips using I.sup.2 L.